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Public repository / OSCPU

NutShell

RISC-V SoC designed by students in UCAS

1.6KStars

262Forks

83Open issues

45Subscribers

Language distribution

Share of source bytes reported by GitHub

Scala56%

Tcl35%

Verilog5%

C2%

Makefile1%

SystemVerilog1%

Linker Script1%

Shell<1%

Python<1%

Recent activity

Latest commits on the default branch

TLB: gate hardware A/D updates behind EnableUpdateAD (#280)good-circle · Sep 20, 2026 TLB: apply in-order A/D page-fault checks to the OoO pathgood-circle · Sep 17, 2026 ready-to-run: bump nemu-sogood-circle · Sep 21, 2026 CSR: add menvcfg and senvcfg as read-only zerogood-circle · Sep 21, 2026 CSR: keep CY/TM/IR writable in counterengood-circle · Sep 19, 2026 CSR: write ebreak PC into xtvalgood-circle · Sep 19, 2026 CSR: fix medeleg write maskgood-circle · Sep 19, 2026

Project details

Created Jul 2020 Updated Sep 2026 Other Project website

Contributors

8

sashimi-yzh739 commits

AugustusWillisWang421 commits

wakafa1118 commits

Lemover108 commits

poemonsense68 commits

good-circle13 commits

CSR: drop unimplemented PMP registersgood-circle · Sep 18, 2026

BPU: sample BTB ready on lookup, not every cycle (#284)good-circle · Sep 20, 2026

CSR: skip minstret on traps (#283)good-circle · Sep 20, 2026

Wonicon

12 commits

klin029 commits