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Public repository / chipsalliance

chisel

Chisel: A Modern Hardware Design Language

4.8KStars

661Forks

517Open issues

150Subscribers

Language distribution

Share of source bytes reported by GitHub

Scala98%

C++1%

Python<1%

JavaScript<1%

Shell<1%

Makefile<1%

CSS<1%

Verilog<1%

SystemVerilog<1%

Nix<1%

C<1%

Recent activity

Latest commits on the default branch

Fix quadratic handling of Definitions (#5506)jackkoenig · Oct 5, 2026 [cd] Bump CIRCT from firtool-1.160.0 to firtool-1.161.0 (#5503)chiselbot · Oct 2, 2026 Enable MiMa for v7.16.0 (#5502)chiselbot · Oct 1, 2026 [Bool] Give a descriptive error when resizing a Bool (#5495)mumallaeng · Oct 1, 2026 [chiseltest] Basic reimplementation of the `verify` function (#5500)dobios · Oct 1, 2026 Fix leaking of DynamicContext state when an exception is thrown (#5501)jackkoenig · Sep 30, 2026 Bump image-size from 2.0.2 to 2.0.4 in /website (#5497)

Project details

Created Apr 2015 Updated Oct 2026 Apache License 2.0 Project website

chip-generatorchiselchisel3firrtlrtlscalaverilog

Contributors

8

jackkoenig1419 commits

seldridge1277 commits

azidar685 commits

ucbjrl392 commits

dependabot[bot]247 commits

dependabot[bot] · Sep 29, 2026

[cd] Bump CIRCT from firtool-1.159.0 to firtool-1.160.0 (#5498)chiselbot · Sep 28, 2026

Preserve literals in Cat (#5492)jackkoenig · Sep 22, 2026

[Data] Distinguish LHS/RHS in connect/bulkConnect hardware error (#5491)mumallaeng · Sep 21, 2026

ducky64

211 commits

sequencer206 commits

scala-steward201 commits