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Public repository / dpretet

cdc

Repository gathering basic modules for CDC purpose

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4Subscribers

Language distribution

Share of source bytes reported by GitHub

SystemVerilog54%

Verilog46%

Forth<1%

Recent activity

Latest commits on the default branch

Fix: correct document link and update explanationsdpretet · Dec 31, 2019 Syntax fixesdpretet · May 5, 2019 Correct file name and link for pulse synchro hskdpretet · May 5, 2019 Update explanationsdpretet · May 5, 2019 Add data bus synchron moduledpretet · Mar 19, 2019 Add a new module hsk pulse synchro module and rename all io with tvalid/tready naming to match AXI4-Streamdpretet · Mar 19, 2019 Add out and vcd extensions into gitignoredpretet · Mar 18, 2019 Add pulse_synchro.v unit testdpretet · Mar 17, 2019 Add basic unit tests for ffd_synchro.vdpretet · Mar 17, 2019 Small comments update in debouncerdpretet · Mar 17, 2019

Project details

Created Mar 2019 Updated Dec 2019 Apache License 2.0

asiccdccross-domain-crossingfgpafifopulse-synchronizertiming

Contributors

1

dpretet14 commits